--
-- VHDL Architecture codec_control2.codec_stimuli.arch
--
-- Created:
--          by - toban963.student (southfork-07.edu.isy.liu.se)
--          at - 13:15:40 10/09/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

ENTITY codec_stimuli IS
   PORT( 
      AUD_ADCDAT  : OUT    std_logic;
      AUD_BCLK    : INOUT  std_logic;
      reset_n     : OUT    std_logic;
      AUD_ADCLRCK : INOUT  std_logic;
      I2C_SDAT    : INOUT  std_logic;
      I2C_SCLK    : IN     std_logic
   );

-- Declarations

END codec_stimuli ;

--
ARCHITECTURE arch OF codec_stimuli IS
SIGNAL DA_left_reg, DA_right_reg: std_logic_vector (0 TO 23);
SIGNAL last_adc: std_logic;
BEGIN
  
PROCESS
BEGIN
AUD_BCLK <= 'Z'; 
AUD_ADCLRCK <= 'Z';
reset_n <= '0' , '1' after 10 ns;
wait;
END PROCESS;
  
  
PROCESS(AUD_BCLK)
variable count: integer range 0 to 26;
variable change_input: integer range -1 to 3;
BEGIN
  Case change_input is
  when -1 =>
--    DA_left_in <= "H1111111" & "11111111" & "11111110";
--    DA_right_in <= "H1111111" & "11111111" & "11111110";
--    DA_left_reg <= "H1111111" & "11111111" & "11111110";
--    DA_right_reg <= "H1111111" & "11111111" & "11111110";
  when 0 =>
--    DA_left_in <= "H1111111" & "11111111" & "11111110";
--    DA_right_in <= "H1111111" & "11111111" & "11111110";
    DA_left_reg <= "11111111" & "00000000" & "11111111";
    DA_right_reg <= "11111111" & "00000000" & "11111111";   
  when 1 =>    
--    DA_left_in <= AD_left_out;
--    DA_right_in <= AD_right_out;
--    DA_left_reg <= AD_left_out;
--    DA_right_reg <= AD_right_out;    
NULL;  
  when 2 =>
--    DA_left_in <= "L1111111" & "11111111" & "1111111W";
--    DA_right_in <= "L1111111" & "11111111" & "1111111W";
    DA_left_reg <= "00000000" & "11111111" & "00000000";
    DA_right_reg <= "00000000" & "11111111" & "00000000"; 
  when 3 =>
--    DA_left_in <= AD_left_out;
--    DA_right_in <= AD_right_out;
--    DA_left_reg <= AD_left_out;
--    DA_right_reg <= AD_right_out;    
  NULL;
  END CASE;
  
  IF AUD_BCLK = '1' THEN
    
    IF AUD_ADCLRCK /= last_adc THEN
      last_adc <= AUD_ADCLRCK;
            count := 0;
    IF last_adc = '1' THEN
      IF change_input < 2 THEN
        change_input := change_input + 1;
      ELSE
        change_input := 0;
      END IF;
    ELSE
      last_adc <= AUD_ADCLRCK;
    END IF;
    END IF;
    
    
    IF count < 24 THEN
    count := count + 1;
    AUD_ADCDAT <= DA_left_reg(count - 1);
    ELSIF count = 25 THEN
   --   count := 0;
    ELSE
      count := count + 1;
    END IF;
  END IF;
END PROCESS;

--PROCESS(I2C_SCLK)
--VARIABLE count: integer range 0 to 9;
--BEGIN
--  IF falling_edge(I2C_SCLK) THEN
--  count := count +1;
--  IF count = 9 THEN
--    I2C_SDAT <= '0';
--    count := 0;
--  ELSE
--    I2C_SDAT <= 'Z';
--  END IF;
--END IF;
--END PROCESS;

I2C_SDAT <= 'Z';
  
END ARCHITECTURE arch;

